Recently, Samsung rolled out a so-called industry-first: a 512 GB DDR5 module. This DDR5 is built on high-dielectric constant (k) metal gate (HKMG) process technology, which will target data-intensive workloads in artificial intelligence (AI), supercomputing, and machine learning (ML) applications.
Samsung’s new DDR5 module for bandwidth-intensive computing in AI and ML applications. Image used courtesy of Samsung
Since 2010, Samsung has used the HKMG process to design logic-based semiconductors to alleviate energy and power dissipation in media-intensive instances for mobile devices. In 2014, Samsung began establishing a dynamic random-access memory (DRAM) portfolio, creating server modules with 256 GB of capacity. Eventually, the DRAM industry required smaller ICs, which required fewer materials to achieve desired design specs.
Samsung’s new DDR5 high-k module represents this accumulation of research experience in HKMG and DRAM processing.
HKMG Process Technology
If semiconductor technologies stay on track with Moore’s Law, transistors will need to shrink while still providing high driving current and high switching capabilities. At some point, manufacturing may come to a halt with standard CMOS process technology.
CMOS fabrication has a recurring obstacle in DRAM development: capacitance. When shrinking transistors, it’s also necessary to decrease gate oxide thickness. However, thinning these materials and layers causes gate leakage current to increase.
Using high-k materials will decrease energy gap levels because it has similar characteristics to thick oxynitride materials. Image used courtesy of Woojin Jeon and Cambridge University
To prevent capacitance issues from becoming design issues, Samsung has sought out material stability—particularly in one to two high-dielectric materials to create low power-consuming ICs for DRAM.
Gate-First vs. Gate-Last Integration Schemes
The first route for utilizing the HKMG process is the “gate-first” approach. This gate-first approach entails an integration scheme that inserts high-dielectric material into the standard CMOS process flow.
The second integration scheme is called “gate-last.” The gate-last approach places the dielectric layer before the gate processing. This placement is advantageous for manufacturers because it involves a low-temperature process that won’t require high thermal activity, which will be cost-effective in the fabrication process. Another benefit of the gate-last scheme is that it is easier to incorporate into traditional CMOS fabrication.
Samsung’s 512 GB DDR5 Module
Samsung’s DDR5 module features eight-layer, through-silicon via (TSV) technology. The company says its HKMG material reduces power consumption by 13% and doubles the speed of DDR4 technology by offering 7,200 Mbps.
An example of TSV used within a chip package. Image used courtesy of Guo et al.
The DDR5 module comprises 32 x 16 GB chips built on a 10nm process that will allow flash memory to take advantage of the high metal functionality from HKMG technology.
Young-Soo Sohn, Samsung’s VP of DRAM memory planning, claims that Samsung is the only semiconductor company with the logic and memory capabilities to incorporate HKMG logic technology into memory development.
Samsung Extends Its DDR5 Portfolio
With Samsung’s extensive DRAM portfolio, other big players such as Intel may work closely with Samsung to increase the market of DDR5-based devices.
In a press release, Carolyn Duran, Intel’s VP and GM of memory and IO technology, also explains, “Intel’s engineering teams closely partner with memory leaders like Samsung to deliver fast, power-efficient DDR5 memory that is performance-optimized and compatible with our upcoming Intel Xeon Scalable processors, code-named Sapphire Rapids.”